This invention relates to a data processing system and more particularly to a DMA (Direct Memory Access) processing system which is capable of improving through-put of the bus over the entire system and expanding utilization of the data bus.
Where it is desired in a computer system to reduce the number of connections to an input/output unit which requires high speed data transfer and the degree of intervention of programs in the input/output operation of data, DMA controlling is effected for direct transfer of data between the input/output unit and a memory.
For example, in a computer system 5 as shown in FIG. 1, a processor 1, a memory 2 and an adaptor 3 are connected to each other through a system bus 4 consisting of an address bus, a data bus and a control bus and in some applications, input/output data exchanged between a data input/output unit 6 and the adaptor 3 is transferred between the memory 2 and the adaptor 3 in a DMA controlling mode. More particularly, the adaptor 3 which is permitted to occupy the system bus 4 starts its internal DMA control circuit so that address codes representative of addresses in the memory 2 to be subjected to DMA control may be sent to the address lines of the system bus 4. When writing data in a DMA mode, the data is sent on the data lines of the bus simulataneously with the delivery of the address.
An 8-bit series in which addressing of memories is effected in one byte unit has been predominant in conventional microcomputers, but in recent years, microcomputers of a 16-bit series have been gaining widespread use. Under the circumstances, in some applications, an 8-bit series microcomputer is connected with a 16-bit series microcomputer and even in a system utilizing a 16-bit data bus, addressing of memories is effected in units of one byte. This means that 8 out of 16 bits for the data bus lie idle.
More particularly, in order to send address codes representative of addresses in the memory 2 to be subjected to DMA control to the address bus, the lower byte in the first word is transferred during the first DMA operation and upper byte in the first word is transferred during the second DMA operation. Similarly, for each of the second and following words a bit is sent in each of two DMA operations. In other words, the DMA cycle must always be repeated twice for transfer of 16-bit data, thus degrading the through-put and effectiveness of the DMA control of the bus.